Shantanu Chakrabartty
Washington University in St Louis, MO·Engineering
Training and running today's artificial intelligence costs enormous amounts of energy: in 2019, training one top-end AI system used more energy than five US cars consume over their whole lifetimes, and the problem has grown. Conventional chips, including central processing units (CPUs), graphics processing units (GPUs) and tensor processing units (TPUs), are not well matched to some of these tasks.
- Fields
Engineering
Computer Science
Physics
- Topics
neuromorphic computing
Ising machine
combinatorial optimization
- Grants
- 3 known grants, through Jun 2029
What they work on
- Model single-electron transport across a Fowler-Nordheim quantum tunneling barrier as the equivalent of a neural spike in NeuroSA, a spiking architecture where neuron firing thresholds follow tunneling physics.
- Validate single-electron transport and the sampling it generates through measurements on floating-gate devices implementing the tunneling barrier, and design self-calibrating circuits that compensate for device mismatch at non-cryogenic temperatures.
- Scale second-order and higher-order Ising machine architectures on a standard semiconductor fabrication process, and solve the problems of coupling tunneling barriers, programming the machine and reading out solutions.
- Connect the dynamics of Fowler-Nordheim Dynamic Analog Memory (FN-DAM) arrays to the training formulations of convolutional neural networks, and develop one-shot continual online learning that exploits those dynamics.
- Design analog compute-in-memory architectures that integrate FN-DAM arrays with CMOS circuits for on-chip adaptation and learning, so computation occurs where weights are stored.
- Validate the hardware-software co-design and its energy-efficiency gains using a large-scale neuromorphic computing research infrastructure and fabricated chip prototypes.
- Build three coordination sub-networks for neuromorphic integrated circuits: behavioral models and simulation software, neuromorphic process design kits using open-source and commercial foundry tools, and shared test infrastructure with benchmarks.
More about the research
An alternative is neuromorphic engineering, which builds circuits that compute the way networks of neurons do, using spikes and physical device dynamics instead of brute-force arithmetic. A recurring ingredient across these projects is Fowler-Nordheim tunneling, a quantum mechanical effect in which individual electrons slip through a thin insulating barrier. Because the effect is slow, precise and extremely low-power, and because it can be built on ordinary silicon manufacturing lines, it can serve either as a source of random spikes or as an analog memory element. One project uses it to solve optimization problems, one uses it to store and update the weights of a learning network, and a third builds a community around designing and testing neuromorphic chips.
Why it matters
If neuromorphic hardware built on ordinary silicon can match or beat conventional processors, it could cut the unsustainable energy cost of training and running AI systems and offer faster, lower-energy solutions to optimization problems in logistics, finance, security, bioinformatics and materials discovery, without requiring the extreme cooling that quantum processors need. The coordination network and open-source design tools directly address a shortage of engineers trained in integrated circuit design, and the projects provide undergraduate and graduate training in AI, neuromorphic and quantum engineering.
Known grants
From NIH and NSF research grants. Labs often have other funding we can't see.
FET: Investigating Neuromorphic ISING Machines using Single-electron Fowler-Nordheim Annealer Network
NSF · Jul 2026 – Jun 2029
RCN-SC: Research Coordination Network for Design and Testing of Neuromorphic Integrated Circuits
NSF · Nov 2023 – Oct 2027
Collaborative Research: FET: Medium: Energy-Efficient Persistent Learning-in-Memory with Quantum Tunneling Dynamic Synapses
NSF · Oct 2022 – Sep 2027
Closest labs
Raisul Islam
Purdue University, IN·Engineering
Fabricate and characterize the Diffusive Ferroelectric Field-Effect Transistor (DFeFET), combining engineered drain contact metals with amorphous oxide semiconductor channels in a ferroelectric-gated transistor to obtain controllable volatile hysteresis in drain current-voltage curves.
Weidong Cao
George Washington University, DC·Engineering
Build AnalogEDA-Hub, an open-source platform with multi-modal datasets, learning-based tools and standard design environments, so researchers can benchmark AI methods for analog circuit design in a reproducible way.
Deliang Fan
Arizona State University Campus Immersion, AZ·Engineering·Early-career
Design, fabricate and validate a hybrid in-memory computing chip that combines RRAM, a non-volatile resistive memory, with SRAM to run deep neural networks with high energy efficiency.
The school
Washington University in St Louis: 97 labs on PI Pages, $1.2B a year on research, 365 research doctorates a year.
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